Microcontroller Chip

Approx. Rs 150 / PieceGet Latest Price

Enhanced Harvard architecture with a high-performance dsPIC30F2010 core and an instruction set architecture optimized by the C compiler.16-bit wide data route and 24-bit wide instructions.30 MIPS or more in operation.DSP Engine for computation-intensive tasks.

• Bit-Reversed and Modulo Addressing modes.
• Two accumulators, each 40 bits wide, with configurable saturation logic.
• Single cycle hardware with 17 bits by 17 bits multiplier for fractions and integers.
• Multiply-Accumulate (MAC) in a single cycle.
• A forty-step Barrel Shifter.
• two-way data fetch.
• Working Environment.
• broad range of operating voltages (2.5V to 5.5V).
• Extended and Industrial Temperature Ranges
• auxiliary elements.
• I/O pins for high current sink/source: 25 mA/25 mA.
• 16-bit timers can be paired with 32-bit timer modules if desired.
• Modules for 3-wire SPITM (supporting 4-frame modes).
• 7-bit/10-bit addressing and Multi-Master/Slave mode are supported by the I2CTM module.
• Modules for Addressable UARTs with FIFO buffers.
• Features of the Motor Control PWM Module.
• PWM Motor Control.
• Independent or Complementary Modes of output.
• Corner and Midway Oriented modes.
• many duty cycle generators.
• Four-mode dedicated time base.
• polarity of the programmable output.
• Deadline management in the complementary mode.
• control of output manually.
• A/D conversion synchronization trigger.
• Features of the Quadrature Encoder Interface Module.

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